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features ? incorporates the arm7tdmi ? arm ? thumb ? processor ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embedded ice in-circuit emulation, debug communication channel support 64 kbytes of internal high-speed flash, organized in 512 pages of 128 bytes ? single cycle access at up to 30 mhz in worst case conditions, prefetch buffer optimi zing thumb instruction execution at maximum speed ? page programming time: 4 ms, including pa ge auto-erase, full erase time: 10 ms ? 10,000 write cycles, 10-year data retentio n capability, sector lock capabilities, flash security bit ? fast flash programming interfa ce for high volume production 16 kbytes of internal high-speed sram , single-cycle access at maximum speed memory controller (mc) ? embedded flash controller, abort status and misalignment detection reset controller (rstc) ? based on power-on reset and low-powe r factory-calibrated brownout detector ? provides external reset signal shaping and reset source status clock generator (ckgr) ? low-power rc oscillator, 3 to 20 mhz on-chip oscillator and one pll power management controller (pmc) ? software power optimization capabilities, including slow clock mode (down to 500 hz) and idle mode ? three programmable external clock signals advanced interrupt controller (aic) ? individually maskable, eight-level priority, vectored interrupt sources ? two external interrupt sources and one fa st interrupt source, spurious interrupt protected debug unit (dbgu) ? 2-wire uart and support for debug communication channel interrupt, programmable ice access prevention periodic interval timer (pit) ? 20-bit programmable counter pl us 12-bit interval counter windowed watchdog (wdt) ? 12-bit key-protected programmable counter ? provides reset or interrupt signals to the system ? counter may be stopped while the processor is in debug state or in idle mode real-time timer (rtt) ? 32-bit free-running counter with alarm ? runs off the internal rc oscillator one parallel input/output controller (pioa) ? thirty-two programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt capability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output eleven peripheral dma controller (pdc) channels one usb 2.0 full sp eed (12 mbits per second) device port ? on-chip transceiver, 328-byte configurable integrated fifos at91 arm ? thumb ? -based microcontrollers AT91SAM7S64 summary preliminary note: this is a summary doc ument. a complete document is available on our web site at www.atmel.com. 6070bs?atarm?25-feb-05
2 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary one synchronous serial controller (ssc) ? independent clock and frame sync sign als for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream ca pabilities with 32-bit data transfer two universal synchronous/asynchrono us receiver transmitters (usart) ? individual baud rate generator, ir da infrared modulation/demodulation ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support ? full modem line support on usart1 one master/slave serial peripheral interface (spi) ? 8- to 16-bit programmable da ta length, four external peripheral chip selects one three-channel 16-bi t timer/counter (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability one four-channel 16-bit pwm controller (pwmc) one two-wire interface (twi) ? master mode support only, all two-wire atmel eeproms supported one 8-channel 10-bit analog-to-digital converter, four channels multiplexed with digital i/os ieee 1149.1 jtag boundary scan on all digital pins 5v-tolerant i/os, including four high-current drive i/o lines, up to 16 ma each power supplies ? embedded 1.8v regulator, drawing up to 10 0 ma for the core and external components ? 3.3v vddio i/o lines power supply, independent 3.3v vddflash flash power supply ? 1.8v vddcore core power supply with brownout detector fully static operation: up to 55 mhz at 1.65v and 85 c worst case conditions available in a 64-lead lqfp package 1. description atmel?s AT91SAM7S64 is a member of a series of low pincount flash microcontrollers based on the 32-bit arm risc processor. it featur es a 64 kbyte high-speed flash and a 16 kbyte sram, a large set of peripherals, including a usb 2.0 device, and a complete set of system functions minimizing the number of external components. the device is an ideal migration path for 8-bit microcontroller users looking fo r additional performance and extended memory. the embedded flash memory can be programmed in-system via the jtag-ice interface or via a parallel interface on a production programmer prior to mounting. built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality. the AT91SAM7S64 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated rc oscillator. the AT91SAM7S64 is a general-purpose microcontroller. its integrated usb device port makes it an ideal device for peripheral applications requiring connectivity to a pc or cellular phone. its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market.
3 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 2. block diagram figure 2-1. AT91SAM7S64 block diagram tdi tdo tms tck nrst fiq irq0-irq1 pck0-pck2 pmc peripheral bridge peripheral dma controller aic pll rcosc sram 16 kbytes arm7tdmi processor ice jtag scan jtagsel pioa usart0 ssc timer counter rxd0 txd0 sck0 rts0 cts0 npcs0 npcs1 npcs2 npcs3 miso mosi spck flash 64 kbytes reset controller drxd dtxd tf tk td rd rk rf tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 memory controller abort status address decoder misalignment detection pio pio apb por embedded flash controller ad0 ad1 ad2 ad3 adtrg pllrc 11 channels pdc pdc usart1 rxd1 txd1 sck1 rts1 cts1 dcd1 dsr1 dtr1 ri1 pdc pdc pdc pdc spi pdc adc advref pdc pdc tc0 tc1 tc2 twd twck twi osc xin xout vddin pwmc pwm0 pwm1 pwm2 pwm3 1.8 v voltage regulator usb device fifo ddm ddp transceiver gnd vddout bod vddcore vddcore ad4 ad5 ad6 ad7 vddflash fast flash programming interface erase pio pgmd0-pgmd15 pgmncmd pgmen0-pgmen2 pgmrdy pgmnvalid pgmnoe pgmck pgmm0-pgmm3 vddio tst dbgu pdc pdc pio pit wdt rtt system controller vddcore
4 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 3. signal description table 3-1. signal description list signal name function type active level comments power vddin voltage regulator power supply input power 3.0v to 3.6v vddout voltage regulator output power 1.85v nominal vddflash flash power supply power 3.0v to 3.6v vddio i/o lines power supply power 3.0v to 3.6v vddcore core power supply power 1.65v to 1.95v vddpll pll power 1.65v to 1.95v gnd ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output pllrc pll filter input pck0 - pck2 programmable clock output output ice and jtag tck test clock input no pull-up resistor tdi test data in input no pull-up resistor tdo test data out output tms test mode select input no pull-up resistor jtagsel jtag selection input pull-down resistor flash memory erase flash and nvm configuration bits erase command input high pull-down resistor reset/test nrst microcontroller reset i/o low pull-up resistor tst test mode select input pull-down resistor debug unit drxd debug receive data input dtxd debug transmit data output aic irq0 - irq1 external interrupt inputs input fiq fast interrupt input input
5 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary pio pa0 - pa31 parallel io controller a i/o pulled-up input at reset usb device port ddm usb device port data - analog ddp usb device port data + analog usart sck0 - sck1 serial clock i/o txd0 - txd1 transmit data i/o rxd0 - rxd1 receive data input rts0 - rts1 request to send output cts0 - cts1 clear to send input dcd1 data carrier detect input dtr1 data terminal ready output dsr1 data set ready input ri1 ring indicator input synchronous serial controller td transmit data output rd receive data input tk transmit clock i/o rk receive clock i/o tf transmit frame sync i/o rf receive frame sync i/o timer/counter tclk0 - tclk2 external clock inputs input tioa0 - tioa2 i/o line a i/o tiob0 - tiob2 i/o line b i/o pwm controller pwm0 - pwm3 pwm channels output spi miso master in slave out i/o mosi master out slave in i/o spck spi serial clock i/o npcs0 spi peripheral chip select 0 i/o low npcs1-npcs3 spi peripheral chip select 1 to 3 output low table 3-1. signal description list (continued) signal name function type active level comments
6 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o analog-to-digital converter ad0-ad3 analog inputs analog digital pulled-up inputs at reset ad4-ad7 analog inputs analog analog inputs adtrg adc trigger input advref adc reference analog fast flash programming interface pgmen0-pgmen2 programming enabling input pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low table 3-1. signal description list (continued) signal name function type active level comments
7 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 4. package and pinout the AT91SAM7S64 is available in a 64-lead lqfp package. 4.1 64-lead lqfp mechanical overview figure 4-1 shows the orientation of the 64-lead lqfp package. a detailed mechanical description is given in the section mechan ical characteristics of the full datasheet. figure 4-1. 64-lead lqfp package pinout (top view) 4.2 pinout 33 49 48 32 17 16 1 64 table 4-1. AT91SAM7S64 pinout in 64-lead lqf package 1 advref 17 gnd 33 tdi 49 tdo 2 gnd 18 vddio 34 pa6/pgmnoe 50 jtagsel 3 ad4 19 pa16/pgmd4 35 pa5/pgmrdy 51 tms 4 ad5 20 pa15/pgmd3 36 pa4/pgmncmd 52 pa31 5 ad6 21 pa14/pgmd2 37 pa27/pgmd15 53 tck 6 ad7 22 pa13/pgmd1 38 pa28 54 vddcore 7 vddin 23 pa24/pgmd12 39 nrst 55 erase 8 vddout 24 vddcore 40 tst 56 ddm 9 pa17/pgmd5/ad0 25 pa25/pgmd13 41 pa29 57 ddp 10 pa18/pgmd6/ad1 26 pa26/pgmd14 42 pa30 58 vddio 11 pa21/pgmd9 27 pa12/pgmd0 43 pa3 59 vddflash 12 vddcore 28 pa11/pgmm3 44 pa2 60 gnd 13 pa19/pgmd7/ad2 29 pa10/pgmm2 45 vddio 61 xout 14 pa22/pgmd10 30 pa9/pgmm1 46 gnd 62 xin/pgmck 15 pa23/pgmd11 31 pa8/pgmm0 47 pa1/pgmen1 63 pllrc 16 pa20/pgmd8/ad3 32 pa7/pgmnvalid 48 pa0/pgmen0 64 vddpll
8 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 5. power considerations 5.1 power supplies the AT91SAM7S64 has six types of power suppl y pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. the six power supply pin types are: vddin pin. it powers the voltage regulator; voltage ranges from 3.0v to 3.6v, 3.3v nominal. if the voltage regulator is not used, vddin should be connected to gnd. vddout pin. it is the output of the 1.8v voltage regulator. vddio pin. it powers the i/o lines and the usb transceivers; dual voltage range is supported. ranges from 3.0v to 3.6v, 3.3v nominal. vddflash pin. it powers a part of the flash and is required for the flash to operate correctly; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddcore pins. they power the logic of the device; voltage ranges from 1.65v to 1.95v, 1.8v typical. it can be connected to the vddout pin with decoupling capacitor. vddcore is required for the device, including its embedded flash, to operate correctly. vddpll pin. it powers the oscillator and the pll. it can be connected directly to the vddout pin. no separate ground pins are provided for the different power supplies. only gnd pins are pro- vided and should be connected as shortly as possible to the system ground plane. 5.2 power consumption the AT91SAM7S64 has a static cu rrent of less than 60 a on vddcore at 25c, including the rc oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. activating the brownout detector adds 20 a static current. the dynamic power consumption on vddcore is less than 50 ma at full speed when running out of the flash. under the same conditions , the power consumption on vddflash does not exceed 10 ma. 5.3 voltage regulator the AT91SAM7S64 embeds a voltage regulator that is managed by the system controller. in normal mode, the voltage regulator consumes less than 100 a static current and draws 100 ma of output current. the voltage regulator also has a low-power mode. in this mode, it consumes less than 20 a static current and draws 1 ma of output current. adequate output supply decoupling is mandatory for vddout to reduce ripple and avoid oscillations. the best way to achi eve this is to use two capacitors in parallel: o ne external 470 pf (or 1 nf) npo capacitor must be connected between vddout and gnd as close to the chip as possible. one external 2.2 f (or 3.3 f) x7r capacitor must be connected between vddout and gnd. adequate input supply decoupling is mandatory for vddi n in order to impr ove startup stability and reduce source voltage drop. the input decoupling capacitor should be placed close to the chip. for example, two capacitors can be used in parallel: 100 nf npo and 4.7 f x7r.
9 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 5.4 typical powe ring schematics 5.4.1 3.3v single supply the AT91SAM7S64 supports a 3.3v single supply mode. the internal regulator is connected to the 3.3v source and its output feeds vddcore and the vddpll. figure 5-1 shows the power schematics to be used for usb bus-powered systems. figure 5-1. 3.3v system single power supply schematic power source ranges from 4.5v (usb) to 18v 3.3v vddin voltage regulator vddout vddio dc/dc converter vddcore vddflash vddpll
10 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 6. i/o lines considerations 6.1 jtag port pins tms, tdi and tck are schmitt trigger inputs. tms and tck are 5-v tolerant, tdi is not. tms, tdi and tck do not integrate a pull-up resistor. tdo is an output, driven at up to vddio, and has no pull-up resistor. the pin jtagsel is used to select the jtag boundary scan when asserted at a high level. the pin jtagsel integrates a permanent pull-down resistor of about 15 k ? to gnd, so that it can be left unconnected for normal operations. 6.2 test pin the pin tst is used for manufacturing test or fast programming mode of the AT91SAM7S64 when asserted high. the pin tst integrates a permanent pull-down resistor of about 15 k ? to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, the tst pin and the pa0 and pa1 pins should be both tied high. driving the tst pin at a high level while pa0 or pa1 is driven at 0 leads to unpredictable results. 6.3 reset pin the pin nrst is bidirectional. it is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. there is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. this allows connection of a simple push-button on the pin nrst as system user reset, and the use of the signal nrst to reset all the components of the system. the pin nrst integrates a permanent pull-up resistor to vddio. 6.4 erase pin the pin erase is used to re-initialize the flash co ntent and some of its nv m bits. it integrates a permanent pull-down resistor of about 15 k ? to gnd, so that it can be left unconnected for normal operations. 6.5 pio controller a lines all the i/o lines pa0 to pa31 are 5v-tolerant and all integrate a programmable pull-up resistor. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. 5v-tolerant means that the i/o lines can drive voltage level according to vddio, but can be driven with a voltage of up to 5.5v. however, driving an i /o line with a voltage over vddio while the programmable pull-up resistor is enabled can lead to unpredictable results. care should be taken, in particular at reset, as all t he i/o lines default to input with pull-up resistor enabled at reset.
11 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 6.6 i/o line drive levels the pio lines pa0 to pa3 are high-drive current capable. each of these i/o lines can drive up to 16 ma permanently. the remaining i/o lines can draw only 8 ma. however, the total current drawn by all the i/o lines cannot exceed 150 ma.
12 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 7. processor and architecture 7.1 arm7tdmi processor risc processor based on armv4t von neumann architecture ? runs at up to 55 mhz, providing 0.9 mips/mhz two instruction sets ?arm ? high-performance 32-bit instruction set ?thumb ? high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e) 7.2 debug and test features integrated embedded in-circuit emulator ? two watchpoint units ? test access port accessible through a jtag protocol ? debug communication channel debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register ieee1149.1 jtag boundary-scan on all digital pins 7.3 memory controller bus arbiter ? handles requests from the arm7tdmi and the peripheral dma controller address decoder provides selection signals for ? three internal 1 mbyte memory areas ? one 256 mbyte embedded peripheral area abort status registers ? source, type and all parameters of the access leading to an abort are saved ? facilitates debug by de tection of bad pointers misalignment detector ? alignment checking of all data accesses ? abort generation in case of misalignment remap command ? remaps the sram in place of the embedded non-volatile memory ? allows handling of dynamic exception vectors embedded flash controller ? embedded flash interface, up to three programmable wait states
13 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary ? prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the required wait states ? key-protected program, erase and lock/unlock sequencer ? single command for erasing, programming and locking operations ? interrupt generation in case of forbidden operation 7.4 peripheral dma controller (pdc) handles data transfer between peripherals and memories eleven channels ? two for each usart ? two for the debug unit ? two for the serial synchronous controller ? two for the serial peripheral interface ? one for the analog-to-digital converter low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory next pointer management for reducing interrupt latency requirements
14 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 8. memory 64 kbytes of flash memory ? 512 pages of 128 bytes ? fast access time, 30 mhz single-cycl e access in worst case conditions ? page programming time: 4 ms, including page auto-erase ? page programming without auto-erase: 2 ms ? full chip erase time: 10 ms ? 10,000 write cycles, 10-yea r data retent ion capability ? 16 lock bits, each protecting 16 sectors of 32 pages ? protection mode to secure contents of the flash 16 kbytes of fast sram ? single-cycle access at full speed 8.1 memory mapping 8.1.1 internal sram the AT91SAM7S64 embeds a high-speed 16-kby te sram bank. after reset and until the remap command is performed, the sram is only accessible at address 0x0020 0000. after remap, the sram also becomes available at address 0x0. 8.1.2 internal flash the AT91SAM7S64 features one bank of 64 kbyt es of flash. at any time, the flash is mapped to address 0x0010 0000. it is also accessible at address 0x0 after the reset and before the remap command. figure 8-1. internal memory mapping 8.2 embedded flash 8.2.1 flash overview the flash of the AT91SAM7S64 is organized in 512 pages of 128 bytes. the 65,536 bytes are organized in 32-bit words. 256m bytes flash before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1 m bytes 1 m bytes 1 m bytes 253 m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000
15 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary the flash contains a 128-byte write buffer, accessible through a 32-bit interface. the flash benefits from the integration of a power reset cell and from the brownout detector. this prevents code corruption during power su pply changes, even in the worst conditions. when flash is not used (read or write access), it is automatically placed into standby mode. 8.2.2 embedded flash controller the embedded flash controller (efc) manages accesses performed by the masters of the system. it enables reading the flash and writing the write buffer. it also contains a user inter- face, mapped within the memory controller on the apb. the user interface allows: programming of the access parameters of the flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, nvm bit set, nvm bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors the embedded flash controller also provides a dual 32-bit prefetch buffer that optimizes 16- bit access to the flash. this is particularly efficient when the proces sor is running in thumb mode. 8.2.3 lock regions the embedded flash controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. the AT91SAM7S64 contains 16 lock regions and each lock region contains 32 pages of 128 bytes. each lock region has a size of 4 kbytes. if a locked-regions erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 16 nvm bits are software programmable through the efc user interface. the command "set lock bit" enables the protection. the command "clear lock bit" unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 8.2.4 security bit feature the AT91SAM7S64 features a security bit, based on a specific nvm-bit. when the security is enabled, any access to the flash, either through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. this security bit can only be enabled, through the command "set security bit" of the efc user interface. disabling the security bit can on ly be achieved by asserting the erase pin at 1, and after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash are permitted. it is important to note that the assertion of the erase pin should always be longer than 50 ms. as the erase pin integrates a permanent pull-dow n, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd for the final application.
16 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 8.2.5 non-volatile brownout detector control two general purpose nvm (gpnvm) bits are us ed for controlling the brownout detector (bod), so that even after a power loss, the brownout detector operations remain as defined by the user. these two gpnvm bits can be cleared or set re spectively through the commands "clear gen- eral-purpose nvm bit" and "set general-pur pose nvm bit" of the efc user interface. gpnvm bit 0 is used as a brownout detector enable bit. setting the gpnvm bit 0 enables the bod, clearing it disables the bod. as serting erase clears the gpnvm bit 0 and thus disables the brownout detector by default. the gpnvm bit 1 is used as a brownout reset enable signal for the reset controller. setting the gpnvm bit 1 enables the brownout reset when a brownout is detected, clearing the gpnvm bit 1 disables the brownout reset. asserting erase disables the brownout reset by default. 8.2.6 calibration bits eight nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user . the erase pin has no effect on the calibration bits. 8.3 fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-handshaked parallel port. it allows gang-pro- gramming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when the tst pin and the pa0 and pa1 pins are all tied high.
17 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 9. system controller the system controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. figure 9-1. system controller block diagram nrst slck advanced interrupt controller real-time timer periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controller por bod rcosc gpnvm[0] cal en power management controller osc pll xin xout pllrc mainck pllck pit_irq mck proc_nreset wdt_irq periph_irq{2] periph_nreset periph_clk[2..14] pck mck pmc_irq udpck nirq nfiq rtt_irq embedded peripherals periph_clk[2] pck[0-2] in out enable arm7tdmi slck slck irq0-irq1 fiq irq0-irq1 fiq periph_irq[4..14] periph_irq[2..14] int int periph_nreset periph_clk[4..14] embedded flash flash_poe jtag_nreset flash_poe gpnvm[0..1] flash_wrdis flash_wrdis proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck gpnvm[1] boundary scan tap controller jtag_nreset ice_nreset debug pck debug idle debug memory controller mck proc_nreset bod_rst_en proc_nreset periph_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset force_ntrst dbgu_txd usb device port udpck periph_nreset periph_clk[11] periph_irq[11] usb_suspend usb_suspend voltage regulator standby voltage regulator mode controller security_bit cal ice_nreset force_ntrst cal
18 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 9.1 system controller mapping the system controller peripherals are all mapped to the highest 4 kbytes of address space, between addresses 0xffff f000 and 0xffff ffff. figure 9-2 shows the mapping of the system controller. note that the memory controller con- figuration user interface is also mapped within this address space. figure 9-2. system controller mapping 9.2 reset controller the reset controller is based on a power-on reset cell and one brownout detector. it gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. in addition, it controls the internal resets and the nrst pin output. it allows to shape a signal on the nrst line, guaranteeing that the length of the pulse meets any requirement. 0xffff f000 0xffff f200 0xffff f1ff 0xffff f3ff 0xffff f5ff 0xffff fbff 0xffff fcff 0xffff feff 0xffff ffff 0xffff f400 0xffff f600 0xffff fc00 0xffff fd0f 0xffff fc2f 0xffff fc3f 0xffff fd4f 0xffff fc6f aic dbgu pioa reserved pmc mc advanced interrupt controller debug unit pio controller a power management controller memory controller 0xffff fd00 0xffff ff00 rstc pit rtt wdt vreg reserved reserved reserved 0xffff fd20 0xffff fd30 0xffff fd40 0xffff fd60 0xffff fd70 reset controller real-time timer periodic interval timer watchdog timer voltage regulator mode controller 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 256 bytes/64 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 256 bytes/64 registers 4 bytes/1 register peripheral name size address peripheral
19 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary note that if nrst is used as a reset output signal for external devic es during power-off, the brownout detector must be activated. 9.2.1 brownout detector and power-on reset the AT91SAM7S64 embeds a brownout detection circuit and a power-on reset cell. both are supplied with and monitor vddcore. both signals are provided to the flash to prevent any code corruption during power-up or power-dow n sequences or if brownouts occur on the vddcore power supply. the power-on reset cell has a limited-accuracy threshold at around 1.5v. its output remains low during power-up until vddcore goes over this voltage level. this signal goes to the reset controller and allows a full re-i nitialization of the device. the brownout detector monitors the vddcore level during operation by comparing it to a fixed trigger level. it secures system operations in the most difficult environments and prevents code corruption in case of brownout on the vddcore. only vddcore is monitored, as a voltage drop on vddflash or any other power supply of the device cannot affect the flash. when the brownout detector is enabled and vddcore decreases to a value belo w the trigger level (vbot-, defined as vbot - hyst/2), the brownout output is immediately activated. when vddcore increases above the trigger leve l (vbot+, defined as vbot + hyst/2), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the threshold voltage has a hysteresis of about 50 mv, to ensure spike free brownout detec- tion. the typical value of the brownout detector threshold is 1.68v with an accuracy of 2% and is factory calibrated. the brownout detector is low-power, as it consumes less than 20 a stat ic current. however, it can be deactivated to save its static current. in this case, it consumes less than 1a. the deactivation is configured through the gpnvm bit 0 of the flash. 9.3 clock generator the clock generator embe ds one low-power rc oscillator, one main oscillator and one pll with the following characteristics: rc oscillator range is between 22 khz and 42 khz main oscillator frequency ranges between 3 and 20 mhz main oscillator can be bypassed pll output ranges between 80 and 220 mhz it provides slck, mainck and pllck.
20 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary figure 9-3. clock generator block diagram 9.4 power management controller the power management controller uses the clock generator outputs to provide: the processor clock pck the master clock mck the usb clock udpck all the peripheral clocks, independently controllable three programmable clock outputs the master clock (mck) is programmable from a few hundred hz to the maximum operating frequency of the device. the processor clock (pck) swit ches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. embedded rc oscillator main oscillator pll and divider clock generator power management controller xin xout pllrc slow clock slck main clock mainck pll clock pllck control status
21 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary figure 9-4. power management co ntroller block diagram 9.5 advanced interrupt controller controls the interrupt lines (nirq and nfiq) of an arm processor individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (rtt, pit, efc, pmc, dbgu, etc.) ? other sources control the peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources ? higher priority interrupts can be served during service of lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations fast forcing ? permits redirecting any interrupt source on the fast interrupt general interrupt mask ? provides processor synchronization on events without triggering an interrupt mck periph_clk[2..14] int udpck usb_suspend slck mainck pllck prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off usb clock controller on/off slck mainck pllck prescaler /1,/2,/4,...,/64 programmable clock controller pllck divider /1,/2,/4 pck[0..2]
22 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 9.6 debug unit comprises: ? one two-pin uart ? one interface for the debug co mmunication channel (dcc) support ? one set of chip id registers ? one interface providing ice access prevention two-pin uart ? implemented features are compatible with the usart ? programmable baud rate generator ? parity, framing and overrun error ? automatic echo, local loopback and remote loopback channel modes debug communication channel support ? offers visibility of commrx and commt x signals from the arm processor chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ? chip id is 0x27090540 (version 0) 9.7 periodic interval timer 20-bit programmable counter plus 12-bit interval counter 9.8 watchdog timer 12-bit key-protected programmable counter running on prescaled slck provides reset or interrupt signals to the system counter may be stopped while the processor is in debug state or in idle mode 9.9 real-time timer 32-bit free-running counter with alarm running on prescaled slck programmable 16-bit prescaler for slck accuracy compensation 9.10 pio controller one pio controller, controlling 32 i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general-purpose i/o) ? input change interrupt ? half a clock period glitch filter ? multi-drive option enables driving in open drain ? programmable pull-up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write
23 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 9.11 voltage regulator controller the aim of this controller is to select the power mode of the voltage regulator between nor- mal mode (bit 0 is cleared) or standby mode (bit 0 is set).
24 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 10. peripherals 10.1 peripheral mapping each peripheral is allocated 16 kbytes of address space. figure 10-1. user peripheral mapping peripheral name size 16 kbytes 16 kbytes 0xfffa 0000 0xfffa 3fff tc0, tc1, tc2 timer/counter 0, 1 and 2 16 kbytes 16 kbytes 16 kbytes reserved 0xfffa 4000 0xf000 0000 twi two-wire interface 0xfffb 8000 usart0 universal synchronous asynchronous receiver transmitter 0 0xfffc 0000 0xfffc 3fff usart1 universal synchronous asynchronous receiver transmitter 1 0xfffc 4000 0xfffc 7fff ssc serial synchronous controller 0xfffd 4000 0xfffd 7fff 0xfffd 3fff 0xfffd ffff spi serial peripheral interface 0xfffe 0000 0xfffe 3fff reserved 0xfffe ffff 0xfffe 4000 0xfffb 4000 0xfffb 7fff reserved 0xfff9 ffff 16 kbytes 0xfffc ffff 0xfffd 8000 0xfffd bfff adc analog-to-digital converter 16 kbytes 0xfffc bfff 0xfffc c000 0xfffb ffff reserved 0xfffb c000 0xfffb bfff pwmc 16 kbytes 0xfffa ffff 0xfffb 0000 0xfffb 3fff udp usb device port 16 kbytes reserved reserved 0xfffd 0000 reserved 0xfffd c000 reserved 0xfffc 8000 pwm controller
25 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 10.2 peripheral multiplexing on pio lines the AT91SAM7S64 features one pio controller, pi oa, that multiplexes the i/o lines of the peripheral set. pio controller a controls 32 lines. each li ne can be assigned to one of two peripheral func- tions, a or b. some of them can also be multiplexed with the analog inputs of the adc controller. table 10-1 on page 26 defines how the i/o lines of the peripherals a, b or the analog inputs are multiplexed on the pio controller a. the two columns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral functions that are output only may be duplicated in the table. all pins reset in their parallel i/o lines function are configured in input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.
26 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 10.3 pio controller a multiplexing table 10-1. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b comments function comments pa0 pwm0 tioa0 high-drive pa1 pwm1 tiob0 high-drive pa2 pwm2 sck0 high-drive pa3 twd npcs3 high-drive pa 4 t w c k t c l k 0 pa5 rxd0 npcs3 pa 6 t x d 0 p c k 0 pa 7 rt s 0 p w m 3 pa8 cts0 adtrg pa9 drxd npcs1 pa10 dtxd npcs2 pa11 npcs0 pwm0 pa12 miso pwm1 pa13 mosi pwm2 pa14 spck pwm3 pa15 tf tioa1 pa16 tk tiob1 pa17 td pck1 ad0 pa18 rd pck2 ad1 pa 1 9 rk fiq ad2 pa 2 0 rf irq0 ad3 pa21 rxd1 pck1 pa22 txd1 npcs3 pa23 sck1 pwm0 pa24 rts1 pwm1 pa 2 5 c t s 1 p w m 2 pa26 dcd1 tioa2 pa27 dtr1 tiob2 pa28 dsr1 tclk1 pa29 ri1 tclk2 pa30 irq1 npcs2 pa31 npcs1 pck2
27 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 10.4 peripheral identifiers the AT91SAM7S64 embeds a wide range of peripherals. table 10-2 defines the peripheral identifiers of the AT91SAM7S64. a peripheral identifier is required for the control of the periph- eral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. note: 1. setting sysirq and adc bits in the clock set/clear register s of the pmc has no effect. the system controller is continuously clocked. t he adc clock is automatic ally started for the first conversion. in sleep mode the adc cl ock is automatically stopped after each conversion. 10.5 serial peripheral interface supports communication with external serial devices ? four chip selects with external dec oder allow communication with up to 15 peripherals ? serial memories, such as dataflash ? and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select table 10-2. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1 sysirq (1) system interrupt 2 pioa parallel i/o controller a 3 reserved 4adc (1) analog-to digital converter 5 spi serial peripheral interface 6us0usart 0 7us1usart 1 8 ssc synchronous serial controller 9 twi two-wire interface 10 pwmc pwm controller 11 udp usb device port 12 tc0 timer/counter 0 13 tc1 timer/counter 1 14 tc2 timer/counter 2 15 - 29 reserved 30 aic advanced interrupt controller irq0 31 aic advanced interrupt controller irq1
28 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? maximum frequency at up to master clock 10.6 two-wire interface master mode only compatibility with standard two-wire serial memories one, two or three bytes for slave address sequential read/write operations 10.7 usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode ? 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb or lsb first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? hardware handshaking rts - cts ? modem signals management dtr-dsr-dcd-ri on usart1 ? receiver time-out and transmitter timeguard ? multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo 10.8 serial synchronous controller provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal , a clock signal and a frame synchronization signal
29 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 10.9 timer counter three 16-bit timer counter channels ? three output compare or two input capture wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs, as defined in table 10-3 ? two multi-purpose input/output signals ? two global registers that act on all three tc channels 10.10 pwm controller four channels, one 16-bit counter per channel common clock generator, providing thirteen different clocks ? one modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs independent channel programming ? independent enable/disable commands ? independent clock selection ? independent period and duty cycl e, with double bufferization ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform 10.11 usb device port usb v2.0 full-speed compliant,12 mbits per second. embedded usb v2.0 full-speed transceiver table 10-3. timer counter clocks assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 mck/1024
30 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary embedded 328-byte dual-port ram for endpoints four endpoints ? endpoint 0: 8 bytes ? endpoint 1 and 2: 64 bytes ping-pong ? endpoint 3: 64 bytes ? ping-pong mode (two memory banks) for bulk endpoints suspend/resume logic 10.12 analog-to-digital converter 8-channel adc 10-bit 100 ksamples/sec. successi ve approximation register adc -2/+2 lsb integral non linearity, -1/+2 lsb differential non linearity integrated 8-to-1 multiplexer, offering eight independent 3.3v analog inputs individual enable and disable of each channel external voltage reference for better accuracy on low voltage inputs multiple trigger source ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels four of eight analog inputs shared with digital signals
31 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 11. ordering information table 11-1. ordering information ordering code package package type rom code revision temperature operating range AT91SAM7S64-au-001 lqfp 64 green 001 industrial (-40c to 85c)
32 6070bs?atarm?25-feb-05 AT91SAM7S64 summary preliminary 12. revision history 13. doc. rev source comments 6070as date: 19-nov-04 6070bs date: 07-jan-04 csr 04-427 pg. 19, pll output range changed csr 05-010 pg. 30, table 6: ordering information. table replaced.
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